The present invention relates to a method of manufacturing a semiconductor device, and, in particular, a method suitable for manufacturing a microstructure bipolar CMOS (Bi CMOS) device.
With the higher integration of semiconductor devices, microstructure are required more and more for each element. An example of semiconductor devices for which a microstructure is required is a Bi CMOS device, in which bipolar transistors and CMOS transistors are arranged on the same substrate, in particular. The conventional method of manufacturing bipolar transistors in a Bi CMOS device will be described below.
FIGS. 3A to 3C show a conventional manufacturing method. First, as shown in FIG. 3A, a buried layer 32 is formed on the surface of a semiconductor substrate 31 by diffusing antimony (Sb). Further, an epitaxial layer 33 is formed on the surface of the buried layer 32 by the silicon epitaxial growth technique. Thereafter, an element separating layer 34 is formed between elements to be formed. A resist is applied on the surface of the element separating layer 34 to form a resist film 35; the obtained resist film 35 is patterned; and a base p.sup.+ region 36 is formed by injecting ions of boron fluoride (BF.sub.2.sup.+) with the resist film 35 as a mask. This base p.sup.+ region 36 is formed to reduce the base resistance.
Thereafter, as shown in FIG. 3B, after the resist film 35 has been removed, a new resist is applied; the obtained resist film is patterned to form a resist film 35a, in which a portion for forming a base p.sup.- region is removed; and the base p.sup.- region 37 is formed by injecting boron ions (B.sup.+), with the resist film 35a as a mask.
Further, as shown in FIG. 3C, the resist film 35a is removed to form an interlayer insulating film 38. After the interlayer insulating film 38 has been patterned by the isotropic reactive ion etching technique, an emitter polysilicon electrode 39 is formed. Further, an emitter layer 40 can be formed by injecting impurity ions such as arsenic (As) into the emitter polysilicon electrode 39 and diffusing the injected impurity ions into the base p.sup.- region 37 by heat treatment. NPN type bipolar transistors are conventionally manufactured in accordance with the above-mentioned method.
In the conventional method, however, since the base p.sup.+ region 36 is formed by patterning the resist film 35, there inevitably exists an offset in the mask matching process. Therefore, a mask matching margin is required between the base p.sup.+ region 36 and the emitter layer 40 under consideration of the inevitable mask matching error. As a result, a relatively large distance of about 2 .mu.m, for instance, is necessary between the base p.sup.+ 36 region and the emitter layer 40, thus, resulting in difficulty in realigning a microstructure element.